1. Field of the Invention
The present invention relates to a structure for isolating photoelectric conversion elements in solid-state image pickup devices.
2. Description of the Related Art
Digital still cameras and camcorders use two-dimensional solid-state image pickup devices such as charge coupled devices (CCD) or amplification-type MOS imagers. Japanese Patent Laid-Open No. 2003-258232 discloses a configuration for improving sensitivity of amplification-type MOS solid-state image pickup devices.
More specifically, Japanese Patent Laid-Open No. 2003-258232 discloses a solid-state image pickup device including a pixel transistor and a photodiode (hereinafter, referred to as a PD) serving as a photoelectric conversion element. The pixel transistor and the PD are provided in an n-type semiconductor region formed on a p-type semiconductor well region to improve sensitivity. Japanese Patent Laid-Open No. 2003-258232 further discloses a configuration including a first p-type semiconductor well region provided under a local oxidation of silicon (LOCOS) layer, and a second p-type semiconductor well region provided under the first p-type semiconductor well region.
The second p-type semiconductor well region is patterned to be smaller and to be spaced farther from the PD than the first p-type semiconductor well region not to suppress the depletion layer area of the PD. Accordingly, the structure improves the sensitivity of the PD.
However, the inventor found the following disadvantages of the configuration disclosed in Japanese Patent Laid-Open No. 2003-258232. The further the pixel is scaled down, the harder the pixel keeps its sensitivity or its isolation performance because of the difficulties of forming the second p-type semiconductor well.
The problem is attributed to the demand for the photoresist thick enough for forming the deep semiconductor region with high energy ion implantation. When the pixel is small, the width of the second semiconductor well region formed under an isolation region must be scaled down. Accordingly, the ratio of the thickness to the width of the photoresist, i.e., the aspect ratio of the opening pattern of the photoresist, increases. To form such a photoresist pattern with large aspect ratio becomes difficult.
Furthermore, the p-type semiconductor well region under the n-type semiconductor region is desired to be formed at a deeper position to keep its sensitivity even when the pixel size is small. However, the second p-type semiconductor well region is hard to correspond to the depth since ion implantation at a high energy level is not available because of the difficulty of the photoresist pattern with the sufficient aspect ratio. If the p-type semiconductor well region under the n-type semiconductor region only deepens, the charge generated in the PD may flow into adjacent pixels, because the p-type semiconductor well region cannot be connected to the second p-type semiconductor well region.
Even if the p-type semiconductor well region can be connected to the second p-type semiconductor well region, charge generated at a deep part of the semiconductor substrate under an element isolation region may easily diffuse into adjacent pixels.